概要

• 給与

  応相談

• 業界

  半導體製造業, 被動電子元件製造業, 光電材料・元件製造業, 其他

• 仕事内容

  【Role Description】
  Join SkyeChip, a leading Malaysian-based semiconductor company focused on cutting-edge ASIC/SoC design and IP development. We are seeking a highly experienced and technically profound Staff
  Design Verification Engineer to take on a technical leadership role in pre-silicon verification for complex, next-generation Application-Specific Integrated Circuits (ASICs). This role is critical in driving verification excellence, setting technical direction, and mentoring local talent.
  
  
  【Key Responsibilities】
  •Verification Strategy & Ownership: Define, implement, and lead the overall verification strategy and test plan development (including functional, coverage, and performance) for complex digital ASIC blocks or full chips, ensuring robust quality before tape-out.
  •Advanced UVM Testbench: Architect, develop, and maintain advanced, reusable UVM-based verification environments using SystemVerilog to enable constrained-random and coverage-driven verification.
  •C/C++ Programming: Develop C/C++ test cases, firmware test cases for efficient hardware/software co-verification via DPI-C.
  •Execution and Triage: Hands-on execution of the verification plan, including test case development, regression management, triage, and expert root-cause analysis of functional bugs in RTL and gate-level simulations.
  •Coverage and Sign-off: Drive and achieve comprehensive functional and code coverage closure goals, utilizing advanced techniques, writing complex assertions (SVA), and ensuring formal verification compliance.
  •Technical Mentorship: Act as a subject matter expert and mentor to junior and intermediate verification engineers, fostering best practices in coding, methodology, and debug techniques across the team.
  •Flow Improvement: Evaluate, select, and develop new verification methodologies, tools, and flows (e.g., formal verification, emulation) to enhance the overall team's productivity and quality.