概要
給与
応相談
業界
半導體製造業, 被動電子元件製造業, 光電材料・元件製造業, 其他
仕事内容
【Role Description】
This is a full-time on-site role based in Penang, for a Senior IP Logic Design Engineer. The engineer will be responsible for the design and implementation of logic design, microarchitecture definition,
RTL coding, ip releases, high speed timing convergence, and collaboration with cross-functional teams to meet project specifications. Tasks also functional validation through black box and white box validation, FPV validation, functional validation as well as emulations.
【Key Responsibilities】
•IP Design Responsibility
・Define and design Unit Level / Layer Level IP Design that able to converge timing at high end process node, with high frequency requirements.
・Ability to produce testplans to cover design requirement
•IP Quality Responsibility
・Ability to execute design validations, FPV, lintra, CDC and etc tools
•IP Releases
・Owning the IP Releases for customer release depending on the assignment
求めている人材
応募条件
【必須条件】
•Strong skills in Logic Design and RTL Coding with Verilog or system Verilog.
•Experience in high-speed timing convergence in various process node.
•Deep understanding of Computer Architecture, memory traffic, io controller such as PCIe or UCIe.
•Excellent problem-solving abilities and attention to detail.
•Ability to work collaboratively with cross-functional teams to get the project completions.
•Ability to execute various IP design tools such as CDC, Lintra, FEV, etc.
【理想人物像】
•Bachelor's or Master's degree in Electronics Engineering, Computer Engineering, or related field.
•Experience in the semiconductor industry for Minimum >5 years’ experience in high speed digital logic design.英語
B/初級商業程度
その他言語
-
その他
福利厚生
【法定項目】
・依照馬來西亞當地法定制度
【公司福利】
・年假：14天起
・病假：14天起
・醫療保險
・牙科／眼科補助：每年 RM500
・門診補助：每年 RM1,000
・績效獎金
・年度調薪雇用形態
全職
就業時間
8:30 ~ 17:30
休日
週休二日
職種
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